suggestion for matchhit settings

I need to navigate between verilog code and I tried few settings with
matchit but I don't have any success.
Problem is I need to match "begin:end", "case:endcase" independently.
I end up getting also match for begin:endcase.

Here is pseudo verilog code
always @(posedge clk) begin
case(index)
1: $display();
default: $error();
endcase
end

Also, Just wondering, anyone has matchit settings for verilog/
systemverilog.

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