答复: some word can't highlight in verilog

Sorry,I am chinese.English is not well.

All ports should be highlight in Verilog's module declaration,But there some ports are not highlight in this picture.
Example :
RSTn
Sig_rx_sys_cs

-----邮件原件-----
发件人: vim_use@googlegroups.com [mailto:vim_use@googlegroups.com] 代表 Christian Brabandt
发送时间: 2012年7月17日 13:44
收件人: vim_use@googlegroups.com
主题: Re: some word can't highlight in verilog

On Tue, July 17, 2012 07:14, 王军 wrote:
>
>
> Like it.

And your question is what?

Please include a brief description of the problem, what you see and what you expect. Remember, not everybody knows verilog, so your screenshot might not tell us much (though I can vaguely guess, what your problem could be).


regards,
Christian

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