for example, a section of verilog code:
// define input and output ports
input A;
output B;
// main logic
wire C;
assign C = A & B;
A,B and C are all treated as variables, so displayed in the same color. I'm wondering if vim can use different color for A and B than C?
--
--
You received this message from the "vim_use" maillist.
Do not top-post! Type your reply below the text you are replying to.
For more information, visit http://www.vim.org/maillist.php
---
You received this message because you are subscribed to the Google Groups "vim_use" group.
To unsubscribe from this group and stop receiving emails from it, send an email to vim_use+unsubscribe@googlegroups.com.
For more options, visit https://groups.google.com/groups/opt_out.
No comments:
Post a Comment