Verilog Ternary Operator

Hello All,

I have run into a problem when using Vim in Verilog and am hoping you can help.
The problem has to do with the ternary operator.

I have a file that looks like this:

wire [31:0] modified_value_w;

...

assign modified_value_w = (some_register_r & read_wire_w);

assign result_w = enable_w?modified_value_w:some_other_wire_w;

When I search for \<modified_value_w\>, Vim only finds this first 2 lines.
this is because the 3rd line doesn't have whitespace around the "?"

Vim treats the "?" Character as a keyword for Verilog,
because it can be part of a number (ex: 16'b? )

My question is: Is there a way to get Vim to treat "?" as a keyword when used in
a number, but not when it's being used as a ternary operator?

Thanks in Advance,
Sean

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