Re: some word can't highlight in verilog

On Tue, July 17, 2012 09:57, 王军 wrote:
> Yes ,you are right!
> If the letters of port are all upper case,it is highlight.
> If the letters of port are not all upper case,it is not highlight.
> Example:
> RSnT
> Signal,and so on.
>
> Thank you very much.
>
> If I want all letters are highlight,what can I do? Modify Verilog.vim?

I think what should work is, create a file verilog.vim in the path
(create non-existing directories):
~/.vim/after/syntax/ (Unix) or
$VIM/vimfiles/after/syntax/ (Windows, where $VIM is whatever Vim tells
you when doing :echo $VIM)

(see also the thread about modifying filetype plugins, that was
discussed here some days ago and in which I mentioned the link
to the faq)

and only put this single line into verilog.vim:
syn match verilogConstant "\<[A-Za-z][A-Za-z0-9_]\+\>"

regards,
Christian

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