Re: some word can't highlight in verilog

Hi,

On Tue, Jul 17, 2012 at 01:14 AM PDT, Christian Brabandt wrote:
CB> On Tue, July 17, 2012 09:57, ?? wrote:
CB> > Yes ,you are right!
CB> > If the letters of port are all upper case,it is highlight.
CB> > If the letters of port are not all upper case,it is not highlight.
CB> > Example:
CB> > RSnT
CB> > Signal,and so on.
CB> >
CB> > Thank you very much.
CB> >
CB> > If I want all letters are highlight,what can I do? Modify Verilog.vim?
CB>
CB> I think what should work is, create a file verilog.vim in the path
CB> (create non-existing directories):
CB> ~/.vim/after/syntax/ (Unix) or
CB> $VIM/vimfiles/after/syntax/ (Windows, where $VIM is whatever Vim tells
CB> you when doing :echo $VIM)
CB>
CB> (see also the thread about modifying filetype plugins, that was
CB> discussed here some days ago and in which I mentioned the link
CB> to the faq)
CB>
CB> and only put this single line into verilog.vim:
CB> syn match verilogConstant "\<[A-Za-z][A-Za-z0-9_]\+\>"

Note that the ports are being highlighted because they are in all caps
and are being treated as if they are constants (typically one would not
use all caps for signals names). Ports--per se--are not processed and
given any specific highlighting.

Regards,

--
Mun

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