how to quickly edit verilog code block?

How to write the second code block quickly? The second's function are same to the first one?

input clk;//clock
input rst_n;//reset
reg [7:0] r_aa;
reg [3:0] r_idx;
///// start first code block
reg [7:0] r_array_00;
reg [7:0] r_array_01;
reg [7:0] r_array_02;
reg [7:0] r_array_03;

always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
r_array_00 <= 8'd0;
r_array_01 <= 8'd0;
r_array_02 <= 8'd0;
r_array_03 <= 8'd0;
end
else begin
case(r_idx)begin
4'd0:begin
r_array_00 <= r_aa;
end
4'd1:begin
r_array_01 <= r_aa;
end
4'd2:begin
r_array_02 <= r_aa;
end
4'd3:begin
r_array_03 <= r_aa;
end
default:
endcase
end
end
///// end first block

//// start second block, it's same to the first block
reg [7:0] r_array_10;
reg [7:0] r_array_11;
reg [7:0] r_array_12;
reg [7:0] r_array_13;

//// end second block

--
--
You received this message from the "vim_use" maillist.
Do not top-post! Type your reply below the text you are replying to.
For more information, visit http://www.vim.org/maillist.php

---
You received this message because you are subscribed to the Google Groups "vim_use" group.
To unsubscribe from this group and stop receiving emails from it, send an email to vim_use+unsubscribe@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.