>
> At least for VHDL, you may check the help:
>
> :h ft-vhdl-indent
>
> :let g:vhdl_indent_genportmap = 0
>
> --
> Andy
>
Thanks Andy. I tried it but it still does not work right. It is not that I
want to change the way it indents the VHDL code, but that the way the plugin
indents the code is simply wrong.
At some point the indenting gets messed up, and things which should be at
the same level of indentation are put in different levels as in the example
files I sent yesterday.
Cheers,
Didly
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